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L6732
Adjustable step-down controller with synchronous rectification
Features

Input voltage range from 1.8V to 14V Supply voltage range from 4.5V to 14V Adjustable output voltage down to 0.6V with 0.8% accuracy over line voltage and temperature (0C~125C) Fixed frequency voltage mode control TON lower than 100ns 0% to 100% duty cycle External input voltage reference Soft-start and inhibit High current embedded drivers Predictive anti-cross conduction control Programmable high-side and low-side RDS(on) sense over-current-protection Selectable switching frequency 250KHz/ 500KHz Pre-bias start up capability Power good output Master/slave synchronization with 180 phase shift Over voltage protection Thermal shut-down Package: HTSSOP16 HTSSOP16 (Exposed Pad)

Applications

LCD & PDP TV High performance / high density DC-DC modules Low voltage distributed DC-DC niPOL converters DDR memory supply Graphic cards
Order codes
Part number L6732 L6732TR Package HTSSOP16 HTSSOP16 Packing Tube Tape & Reel
September 2006
Rev 5
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Contents
L6732
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 4 5
Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 12 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.13.1 Fan's power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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L6732
Contents
6
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 6.2 6.3 6.4 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
L6732 demoboards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 7.2 20A board description and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5A board description and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Summary description
L6732
1
Summary description
The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPOL converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600mV with a maximum tolerance of 0.8% and it is also possible to use an external reference from 0V to 2.5V. The input voltage can range from 1.8V to 14V, while the supply voltage can range from 4.5V to 14V. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A. The PWM duty cycle can range from 0% to 100% with a minimum on-time (TON, MIN) lower than 100ns making possible conversions with very low duty cycle at high switching frequency. The device provides voltage-mode control that includes a selectable frequency oscillator (250KHz or 500KHz). The error amplifier features a 10MHz gain-bandwidth-product and 5V/s slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the RDS(ON) of both the high-side and low-side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions. When necessary, two different current limit protections can be externally set through two external resistors. During the soft-start phase a constant current protection is provided while after the soft-start the device enters in hiccup mode in case of over-current. During the soft-start, the sink mode capability is disabled in order to allow a proper start-up also in pre-biased output voltage conditions. After the soft-start the device can sink current. Other features are Power-Good, Master/Slave synchronization (with 180 phase shift), over-voltage-protection, feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the realization of really compact DC/DC converters.
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L6732
Summary description
1.1
Figure 1.
Functional description
Block diagram
Vcc=4.5V-14V Vin=1.8V-14V
OCL
OCH
VCCDR
BOOT
LDO
SS
Monitor Protection and Ref
HGATE
OSC
EAREF
-
PHASE
VOUT
L6732
PGOOD
LGATE
+ -
0.6V
+
PWM E/A
+ -
PGND
SYNCH
GND
FB
COMP
5/36
Electrical data
L6732
2
2.1
Table 1.
Electrical data
Maximum rating
Absolute maximum ratings
Parameter VCC to GND and PGND, OCH, PGOOD Value -0.3 to 18 0 to 6 0 to VBOOT - VPHASE BOOT PHASE VPHASE PHASE Spike, transient < 50ns (FSW = 500KHz) SS, FB, EAREF, SYNC, OCL, LGATE, COMP, VCCDR OCH Pin PGOOD Pin OTHER PINS Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002 "Human Body Model" Acceptance Criteria: "Normal Performance" -0.3 to 24 -1 to 18 -3 +24 -0.3 to 6 1500 1000 2000 V V V Unit V V V V Symbol VCC
VBOOT - VPHASE Boot Voltage VHGATE - VPHASE VBOOT
2.2
Table 2.
Thermal data
Thermal data
Description Thermal Resistance Junction to Ambient Storage temperature range Junction operating temperature range Ambient operating temperature range Value 50 -40 to +150 -40 to +125 -40 to +85 Unit C/W C C C
Symbol RthJA TSTG TJ TA
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L6732
Pin connections and functions
3
Figure 2.
Pin connections and functions
Pins connection ( top view)
PGOOD SYNCH
1 2 3 4
5
16 15 14 13 12 11 10 9
VCC VCCDR LGATE PGND BOOT HGATE PHASE
SGND
FB COMP SS/INH EAREF
6 7 8
OCL
OCH
HTSSOP16
Table 3.
Pin n.
Pin functions
Name Function This pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up this pin to VCCDR with a 10K resistor to obtain a logical signal. It is a Master-Slave pin. Two or more devices can be synchronized by simply connecting the SYNCH pins together. The device operating with the highest FSW will be the Master. The Slave devices will operate with 180 phase shift from the Master. The best way to synchronize devices together is to set their FSW at the same value. If it is not used the SYNCH pin can be left floating. All the internal references are referred to this pin. This pin is connected to the error amplifier inverting input. Connect it to VOUT through the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage conditions and the PGood signal. This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. The soft-start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces a current of 10 A through the capacitor. When the voltage at this pin is lower than 0.5V the device is disabled.
1
PGOOD
2
SYNCH
3 4
SGND FB
5
COMP
6
SS/INH
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Pin connections and functions
L6732
Table 3.
Pin n.
Pin functions
Name Function By setting the voltage at this pin is possible to select the internal/external reference and the switching frequency: VEAREF 0-80% of VCCDR -> External Reference/FSW=250KHz
7
EAREF
VEAREF = 80%-95% of VCCDR -> VREF = 0.6V/FSW=500KHz VEAREF = 95%-100% of VCCDR -> VREF = 0.6V/FSW=250KHz An internal clamp limits the maximum VEAREF at 2.5V (typ.). The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100A (IOCL) from this pin to ground through the external resistor (ROCL). The over-current threshold is given by the following equation:
8
OCL
I OCL * I OCL I VALLEY = -------------------------------2 * R DSONLS Connecting a capacitor from this pin to GND helps in reducing the noise injected from VCC to the device, but can be a low impedance path for the high-frequency noise related to the GND. Connect a capacitor only to a "clean" GND. A resistor connected from this pin and the high-side MOSFET(s) drain sets the peakcurrent-limit. The peak current is sensed through the high-side MOSFET(s). The internal 100A current generator (IOCH) sinks a current from the drain through the external resistor (ROCH). The over-current threshold is given by the following equation: I OCH * R OCH I PEAK = --------------------------------R DSONHS
9
OCH
10 11 12 13 14 15 16
PHASE HGATE BOOT PGND LGATE VCCDR VCC
This pin is connected to the source of the high-side MOSFET(s) and provides the return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL. This pin is connected to the high-side MOSFET(s) gate. Through this pin is supplied the high-side driver. Connect a capacitor from this pin to the PHASE pin and a diode from VCCDR to this pin (cathode versus BOOT). This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device. This pin is connected to the low-side MOSFET(s) gate. 5V internally regulated voltage. It is used to supply the internal drivers. Filter it to ground with at least 1F ceramic cap. Supply voltage pin. The operative supply voltage range is from 4.5V to 14V.
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L6732
Electrical characteristics
4
Electrical characteristics
VCC = 12V, TA = 25C, unless otherwise specified.
Table 4.
Symbol
Electrical characteristics
Parameter Test condition Min. Typ. Max. Unit
VCC supply current VCC Stand by current ICC VCC quiescent current OSC = open; SS to GND OSC= open; HG = open, LG = open, PH=open 7 8.5 9 mA 10
Power-ON VCC Turn-ON VCC threshold Turn-OFF VCC threshold VIN OK VIN OK Turn-ON VOCH threshold Turn-OFF VOCH threshold VOCH = 1.7V VOCH = 1.7V 4.0 3.6 1.1 0.9 4.2 3.8 1.25 1.05 4.4 4.0 1.47 1.27 V V V V
VCCDR regulation VCCDR voltage Soft start and inhibit ISS Oscillator fOSC VOSC 237 Accuracy 450 Ramp Amplitude 500 2.1 550 KHz V 250 263 KHz SS = 2V Soft Start Current SS = 0 to 0.5V 20 30 45 7 10 13 A VCC = 5.5V to 14V IDR = 1mA to 100mA 4.5 5 5.5 V
Output voltage VFB Output Voltage VDIS = 0 to Vth 0.597 0.6 0.603 V
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L6732
Table 4.
Symbol Error amplifier REAREF IFB Ext Ref Clamp VOFFSET GV GBWP SR Gate drivers RHGATE_ON High Side Source Resistance VBOOT - VPHASE = 5V VBOOT - VPHASE = 5V VCCDR = 5V VCCDR = 5V Error amplifier offset Open Loop Voltage Gain Gain-Bandwidth Product Slew-Rate Vref = 0.6V Guaranteed by design Guaranteed by design COMP = 10pF Guaranteed by design EAREF Input resistance I.I. bias current Vs. GND VF = 0V 2.3 -5 70
Electrical characteristics
Electrical characteristics
Parameter Test condition Min. Typ. Max. Unit
100 0.290
150 0.5
k A V
+5 100 10 5
mV dB MHz V/s
1.7 1.12 1.15 0.6

RHGATE_OFF High Side Sink Resistance RLGATE_ON Low Side Source Resistance
RLGATE_OFF Low Side Sink Resistance Protections IOCH IOCL OCH Current Source OCL Current Source
VOCH = 1.7V
90 90
100 100 120
110 110
% %
VFB Rising OVP Over Voltage Trip (VFB / VEAREF) VEAREF = 0.6V VFB Falling VEAREF = 0.6V Power Good OCH Current Source OCL Current Source OVP Over Voltage Trip (VFB / VEAREF) VFB Rising VEAREF = 0.6V VOCH = 1.7V 90 90
117
100 100 120
110 110
%
Table 5.
Symbol
Thermal characteristics (VCC = 12V)
Parameter Test condition Min. Typ. Max. Unit
Output voltage VFB Output Voltage TJ = 0C~ 125C TJ = -40C~ 125C 0.596 0.593 0.6 0.6 0.605 V 0.605
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L6732
Device description
5
5.1
Device description
Oscillator
The switching frequency can be fixed to two values: 250KHz or 500KHz by setting the proper voltage at the EAREF pin (see Table 3. Pins function and section 4.3 Internal and external reference).
5.2
Internal LDO
An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5V) is the VCCDR pin (Figure 3.).
Figure 3.
LDO block diagram.
4.5/14V
LDO
The LDO can be by-passed, providing directly a 5V voltage to VCCDR. In this case VCC and VCCDR pins must be shorted together as shown in Figure 4. VCCDR pin must be filtered with at least 1F capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor. VCCDR also represents a voltage reference for PGOOD pin (see Table 3. Pins Function).
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Device description
L6732
5.3
Bypassing the LDO to avoid the voltage drop with low Vcc
If VCC 5V the internal LDO works in dropout with an output resistance of about 1 The . maximum LDO output current is about 100mA and so the output voltage drop is 100mV, to avoid this the LDO can be bypassed.
Figure 4.
Bypassing the LDO
5.4
Internal and external references
It is possible to set the internal/external reference and the switching frequency by setting the proper voltage at the EAREF pin. The maximum value of the external reference depends on the VCC: with VCC = 4V the clamp operates at about 2V (typ.), while with VCC greater than 5V the maximum external reference is 2.5V (typ.).

VEAREF from 0% to 80% of VCCDR -> External reference/Fsw=250KHz VEAREF from 80% to 95% of VCCDR -> VREF = 0.6V/Fsw=500KHz VEAREF from 95% to 100% of VCCDR -> VREF = 0.6V/Fsw=250KHz
Providing an external reference from 0V to 450mV the output voltage will be regulated but some restrictions must be considered:

The minimum OVP threshold is set at 300mV; The under-voltage-protection doesn't work; The PGOOD signal remains low;
To set the resistor divider it must be considered that a 100K pull-down resistor is integrated into the device (see Figure 5.). Finally it must be taken into account that the voltage at the EAREF pin is captured by the device at the start-up when VCC is about 4V.
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L6732
Device description
5.5
Figure 5.
Error amplifier
Error amplifier reference
5.6
Soft start
When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is 35A and charges the capacitor up to 0.5V. After that it becomes 10A until the final charge value of approximately 4V (see Figure 6). The output of the error amplifier is clamped with this voltage (VSS) until it reaches the programmed value. No switching activity is observable if VSS is lower than 0.5V and both MOSFETs are OFF. When VSS is between 0.5V and 1.1V the low-side MOSFET is turned on because the comp signal is lower than the valley of the triangular wave and so the duty-cycle is 0%. As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) even the high-side MOSFET begins to switch and the output voltage starts to increase. The L6732 can only source current during the soft-start phase in order to manage the prebias start-up applications. This means that when the start-up occurs with output voltage greater than 0V (pre-bias startup), even when Vss is between 0.5V and 1.1V the low-side MOSFET is kept OFF (see Figure 7 and Figure 8).
13/36
Device description
L6732
Figure 6.
Device start-up: voltage at the SS pin.
Vc c V in 4V .2 15 .2 V
VCC VIN
Vs s 4 V
t
0V .5
t
Figure 7. Start-up without pre-bias LGate
VOUT IL
VSS
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L6732
Figure 8. Start-up with pre-bias
LGate
Device description
VOUT
IL
VSS
The L6732 can sink or source current after the soft-start phase (see Figure 9.). If an over current is detected during the soft-start phase, the device provides a constant-currentprotection. In this way, in case of short soft-start time and/or small inductor value and/or high output capacitors value and so, in case of high ripple current during the soft-start, the converter can start in any case, limiting the current (see section 4.6 Monitoring and protections) but not entering in HICCUP mode. Figure 9. Inductor current during and after soft-start. VOUT VSS VCC IL
During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
15/36
Device description
L6732
5.7
Driver section
The high-side and low-side drivers allow using different types of power MOSFETs (also multiple MOSFETs to reduce the RDSON), maintaining fast switching transitions. The low-side driver is supplied by VCCDR while the high-side driver is supplied by the BOOT pin. A predictive dead time control avoids MOSFETs cross-conduction maintaining very short dead time duration in the range of 20ns. The control monitors the phase node in order to sense the low-side body diode recirculation. If the phase node voltage is less than a certain threshold (-350mV typ.) during the dead time, it will be reduced in the next PWM cycle. The predictive dead time control doesn't work when the high-side body diode is conducting because the phase node doesn't go negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates.
5.8
Monitoring and protections
The output voltage is monitored by means of pin FB. If it is not within 10% (typ.) of the programmed value, the Power-Good (PGOOD) output is forced low. The device provides over-voltage-protection: when the voltage sensed on FB pin reaches a value 20% (typ.) greater than the reference, the low-side driver is turned on as long as the over voltage is detected (see Figure 10.).
Figure 10. OVP
LGate
FB
It must be taken into account that there is an electrical network between the output terminal and the FB pin and therefore the voltage at the pin is not a perfect replica of the output voltage. However due to the fact that the converter can sink current, in the most of cases the low-side will turn-on before the output voltage exceeds the over-voltage threshold, because the error amplifier will throw off balance in advance. Even if the device doesn't report an over-voltage, the behavior is the same, because the low-side is turned-on immediately. The following figure shows the device behavior during an over-voltage event. The output voltage rises with a slope of 100mV/s, emulating in this way the breaking of the high-side MOSFET as an over-voltage cause.
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L6732
Device description
Figure 11. OVP: the low-side MOSFET is turned-on in advance.
VOUT 109% VFB
LGate
The device realizes the over-current-protection (OCP) sensing the current both on the high-side MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see OCH pin and OCL pin in Table 3. Pins function):

Peak Current Limit Valley Current Limit
The Peak Current Protection is active when the high-side MOSFET(s) is turned on, after a masking time of about 100ns. The valley-current-protection is enabled when the low-side MOSFET(s) is turned on after a masking time of about 400ns. If, when the soft-start phase is completed, an over current event occurs during the on time (peak-current-protection) or during the off time (valley-current-protection) the device enters in HICCUP mode: the high-side and low-side MOSFET(s) are turned off, the soft-start capacitor is discharged with a constant current of 10A and when the voltage at the SS pin reaches 0.5V the soft-start phase restarts. During the soft-start phase the OCP provides a constant-current-protection. If during the TON the OCH comparator triggers an over current the high-side MOSFET(s) is immediately turned off (after the masking time and the internal delay) and returned on at the next pwm cycle. The limit of this protection is that the TON can't be less than masking time plus propagation delay because during the masking time the peak-current-protection is disabled. In case of very hard short circuit, even with this short TON, the current could escalate. The valley-current-protection is very helpful in this case to limit the current. If during the off-time the OCL comparator triggers an over current, the high-side MOSFET(s) is not turned on until the current is over the valleycurrent-limit. This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will be skipped, guaranteeing a maximum current due to the following formula:
I MAX = IVALLEY +
Vin - Vout TON , MIN L
(4)
In constant current protection a current control loop limits the value of the error amplifier output (comp), in order to avoid its saturation and thus recover faster when the output returns in regulation. Figure 12. shows the behaviour of the device during an over current condition that persists also in the soft-start phase.
17/36
Device description
L6732
5.9
HICCUP mode during an OCP
VSS
Figure 12. Constant current and Hiccup mode during an OCP.
VCOMP
IL
5.10
Thermal shutdown
When the junction temperature reaches 150C 10C the device enters in thermal shutdown. Both MOSFETs are turned off and the soft-start capacitor is rapidly discharged with an internal switch. The device doesn't restart until the junction temperature goes down to 120C and, in any case, until the voltage at the soft-start pin reaches 500mV.
5.11
Synchronization
The presence of many converters on the same board can generate beating frequency noise. To avoid this it is important to make them operate at the same switching frequency. Moreover, a phase shift between different modules helps to minimize the RMS current on the common input capacitors. Figure 13 and Figure 14 shows the results of two modules in synchronization. Two or more devices can be synchronized simply connecting together the SYNCH pins. The device with the higher switching frequency will be the Master while the other one will be the Slave. The Slave controller will increase its switching frequency reducing the ramp amplitude proportionally and then the modulator gain will be increased.
18/36
L6732
Figure 13. Synchronization: PWM Signal
Device description
Figure 14. Synchronization: Inductor currents
To avoid a huge variation of the modulator gain, the best way to synchronize two or more devices is to make them work at the same switching frequency and, in any case, the switching frequencies can differ for a maximum of 50% of the lowest one. If, during synchronization between two (or more) L6732, it's important to know in advance which the master is, it's timely to set its switching frequency at least 15% higher than the slave. Using an external clock signal (fEXT) to synchronize one or more devices that are working at a different switching frequency (fSW) it is recommended to follow the below formula:
f SW f EXT 1,3 f SW
(5)
The phase shift between master and slaves is approximately 180.
19/36
Device description
L6732
5.12
Minimum on-time (TON, MIN)
The device can manage minimum on-times lower than 100ns. This feature comes down from the control topology and from the particular over-current-protection system of the L6732. In fact, in a voltage mode controller the current has not to be sensed to perform the regulation and, in the case of L6732, neither for the over-current protection, given that during the off-time the valley-current-protection can operate in every case. The first advantage related to this feature is the possibility to realize extremely low conversion ratios. Figure 15 shows a conversion from 14V to 0.3V at 500KHz with a TON of about 50ns.
Figure 15. 14V -> 0.3V@500KHz, 5A VOUT
IL
VPHASE
50ns
The on-time is limited by the turn-on and turn-off times of the MOSFETs.
20/36
L6732
Device description
5.13
Bootstrap anti-discharging system
This built-in system avoids that the voltage across the bootstrap capacitor becomes less than 3.3V. An internal comparator senses the voltage across the external bootstrap capacitor keeping it charged, eventually turning-on the low-side MOSFET for approximately 200ns. If the bootstrap capacitor is not enough charged the high-side MOSFET cannot be effectively turnedon and it will present a higher RDSON. In some cases the OCP can be also triggered. The bootstrap capacitor can be discharged during the soft-start in case of very long soft-start time and light loads. It's also possible to mention one application condition during which the bootstrap capacitor can be discharged:
5.13.1 Fan's power supply
In many applications the FAN is a DC MOTOR driven by a voltage-mode DC/DC converter. Often only the speed of the MOTOR is controlled by varying the voltage applied to the input terminal and there's no control on the torque because the current is not directly controlled. In order to vary the MOTOR speed the output voltage of the converter must be varied. The L6732 has a dedicated pin called EAREF (see the related section) that allows providing an external reference to the non-inverting input of the error-amplifier. In these applications the duty cycle depends on the MOTOR's speed and sometimes 100% has to be set in order to go at the maximum speed. Unfortunately in these conditions the bootstrap capacitor can not be recharged and the system cannot work properly. Some PWM controller limits the maximum duty-cycle to 80-90% in order to keep the bootstrap cap charged but this make worse the performance during the load transient. Thanks to the "bootstrap antidischarging system" the L6732 can work at 100% without any problem. The following picture shows the device behaviour when input voltage is 5V and 100% is set by the external reference. Figure 16. 100% duty cycle operation
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Application details
L6732
6
6.1
Application details
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current (IL) between 20% and 30% of the maximum output current. The inductance value can be calculated with the following relationship:
L
Vin - Vout Vout Fsw I L Vin
(6)
Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 17. shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5V and VIN = 12V at a switching frequency of 500KHz. Figure 17. Inductor current ripple.
INDUCT O R CURRE NT RIP P L
8 7 6 5 4 3 2 1 0 0 1 2 3 4 O UT P UT V O L T AG E (V )
V in = 1 2 V , L = 1 u H
V in = 1 2 V , L = 2 u H V in = 5 V , L = 5 0 0 n H V in = 5 V , L = 1 .5 u H
Increasing the value of the inductance reduces the ripple current but, at the same time, increases the converter response time to a load transient. If the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100% or to 0%. When one of these conditions is reached, the response time is limited by the time required to change the inductor current. During this time the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitor size.
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L6732
Application details
6.2
Output capacitors
The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During a load transient, the output capacitors supply the current to the load or absorb the current stored in the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100% or 0%, the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):
Vout ESR = Iout ESR
(7)
Moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas:
VoutCOUT =
Iout 2 L 2 Cout (Vin, min D max - Vout )
(8)
VoutCOUT =
Iout 2 L 2 Cout Vout
(9)
Formula (8) is valid in case of positive load transient while the formula (9) is valid in case of negative load transient. DMAX is the maximum duty cycle value that in the L6732 is 100%. For a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum ESR and a minimum COUT value can be set. The ESR and COUT values also affect the static output voltage ripple. In the worst case the output voltage ripple can be calculated with the following formula:
Vout = I L ( ESR +
1 ) 8 Cout Fsw
(10)
Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor discharge is almost negligible.
6.3
Input capacitors
The input capacitors have to sustain the RMS current flowing through them, that is:
Irms = Iout D (1 - D)
(11)
Where D is the duty cycle. The equation reaches its maximum value, IOUT /2 with D = 0.5. The losses in worst case are:
P = ESR (0.5 Iout ) 2
(12)
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Application details
L6732
6.4
Compensation network
The loop is based on a voltage mode control (Figure 18.). The output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulsewidth modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is filtered by the output filter. The modulator transfer function is the small signal transfer function of VOUT/ VCOMP. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor's ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage: VOSC.
Figure 18. Compensation Network
The compensation network consists in the internal error amplifier, the impedance networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fastest transient response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade slope and a phase margin greater than 45. To locate poles and zeroes of the compensation networks, the following suggestions may be used:
Modulator singularity frequencies:
LC =
1 L Cout
(13)
ESR =
1 ESR Cout
(14)
Compensation network singularity frequencies:
P1 =
1 (15) C18 C19 R5 C +C 19 18
1 R5 C19
(17)
P 2 =
1 R4 C20
(16)
Z 1 =
Z 2 =
1 C20 (R3 + R4 )
(18)
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L6732
Application details
Compensation network design: - Put the gain R5/R3 in order to obtain the desired converter bandwidth
C =
- - - - -
R5 Vin LC (19) R3 Vosc
Place before the output filter resonance ; Z1 LC Place at the output filter resonance ; Z2 LC Place at the output capacitor ESR zero ; P1 ESR Place at one half of the switching frequency; P2 Check the loop gain considering the error amplifier open loop gain.
Figure 19. Asymptotic Bode plot of Converter's open loop gain
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L6732 demoboards
L6732
7
7.1
L6732 demoboards
20A board description and PCB layout
L6732 20A demoboard realizes in a four layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from 4.5V to 14V and the output voltage is at 3.3V. The module can deliver an output current in excess of 20A. The switching frequency is set at 250KHz (controller free-running Fsw) but it can be set to 500KHz acting on the EAREF pin.
Figure 20. Demoboard schematic
V IN D 1 J1 R 5 G IN R 6 J2 E TR F XE
ERF AE
R 9
C 9
C 11 C 12-C 3 1
C 10
VCR CD BO OT OH C
15 7
12
9 11 10 14
R 11
HAE GT
Q 4-6 C 5
VC C PA H SE
L 1 VU OT
R 10
L AE GT
R 12 D 3 C 15 C 16-C 19 GU OT
VC C VCR CD R 13 C 8 R 8 C 7 POD GO
16
GD N
3
U 1 L 6732
Q 1-3 13
PG D N
PG O OD
1
SS
6 C 4
SNH YC
SY C NH
2 8
OL C
5
CM OP
4
VB F
R 3 R 7 C 2 R 4 C 3 R 2 R 1 C 1
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L6732
L6732 demoboards
Table 6.
Demoboard part list
Value 1k 1k 4K7 2k7 0 N.C. 2K 10 1K5 2.2 2.2 N.C. 10K 4.7nF 47nF 1nF 100nF 100nF N.C. 100nF 4.7uF 20V 1nF 1uF 220nF 3X 15uF N.C. 2X 330uF 1.8uH STPS1L30M STPS1L30M STS12NH3LL STS25NH3LL L6732 Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Kemet Kemet Kemet Kemet Kemet / Kemet AVX Kemet Kemet Kemet / / / Panasonic ST ST ST ST ST SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 / SMD 0603 SMA6032 SMD 0603 SMD 0603 SMD 0603 / / / SMD DO216AA DO216AA SO8 SO8 HTSSOP16 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD / IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD ST (TDK) / ST (poscap) ST ST ST ST ST ST Manufacturer Neohm Neohm Package SMD 0603 SMD 0603 Supplier IFARCAD IFARCAD
Reference R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12-13 C15 C16-19 L1 D1 D3 Q1-Q2 Q4-Q5 U1
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L6732
Table 7.
Other inductor manufacturer
Series 744318180 CDEP134-2R7MC-H HPI_13 T640 SPM12550T-1R0M220 FDA1254 HCF1305-1R0 Inductor Value (H) 1.8 2.7 1.4 1 2.2 1.15 1.3 Saturation Current (A) 20 15 22 22 14 22 27
Manufacturer WURTH ELEKTRONIC SUMIDA EPCOS TDK TOKO COILTRONICS
HC5-1R0
Table 8.
Other capacitor manufacturer
Series C4532X5R1E156M TDK C3225X5R0J107M 100 100 100 6.3 25 6.3 Capacitor value(F) 15 Rated voltage (V) 25
Manufacturer
NIPPON CHEMI-CON PANASONIC
25PS100MJ12 ECJ4YB0J107M
Figure 21. Demoboard efficiency
Fsw =400K H z
fsw = 500kHz
9 5 .0 0 % E F F IC IE N 9 0 .0 0 %
VIN = 5V
8 5 .0 0 % 8 0 .0 0 %
VIN = 12V
7 5 .0 0 % 1 3 5 7 I o u t (A ) 9 11 13 15
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L6732 demoboards
Figure 22. Top layer
Figure 23. Power ground layer
Figure 24. Signal-ground layer
Figure 25. Bottom layer
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L6732 demoboards
L6732
7.2
5A board description and PCB layout
L6732 5A demoboard realizes in a two layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from 4.5V to 14V and the output voltage is at 3.3V. The module can deliver an output current of up to 5A. The switching frequency is set at 250KHz (controller free-running FSW) but it can be set to 500KHz acting on the EAREF pin. Compared to the 20A version, the only difference of this board, compared to the first one, is the presence of a dual mosfet chip, for the High-side and Low-side Mosfets; besides R15 has been inserted between High side mosfet Gate and Phase pin; R14 has been inserted between Low side mosfet Gate and Pgnd pin.
Table 9.
Demoboard part list
Value 1k 1k 4K7 2k7 0 N.C. 4K99 10 2K49 2.2 2.2 N.C. 10K N.C. N.C. 4.7nF 47nF 1nF 100nF 100nF N.C. 100nF 4.7uF 20V 1nF 1uF Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Kemet Kemet Kemet Kemet Kemet / Kemet AVX Kemet Kemet SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 / SMD 0603 SMA6032 SMD 0603 SMD 0603 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD / IFARCAD IFARCAD IFARCAD IFARCAD Manufacturer Neohm Neohm Package SMD 0603 SMD 0603 Supplier IFARCAD IFARCAD
Reference R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
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L6732
Table 9. Demoboard part list
Value 220nF 3X 10uF N.C. 2X 330uF 2,7uH DO3316P-272HC STPS1L30M STPS1L30M STS8DNH3LL (Dual Mosfet) L6732 Manufacturer Kemet / / / Coilcraft ST ST ST ST Package SMD 0603 / / / SMD DO216AA DO216AA SO8 HTSSOP16
L6732 demoboards
Reference C11 C12-13 C15 C16-19 L1 D1 D3 Q1 U1
Supplier IFARCAD ST (TDK) / ST (poscap) ST ST ST ST ST
Figure 26. Demoboard efficiency
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L6732 demoboards
L6732
Figure 27. Top layer
Figure 28. Power ground layer
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L6732
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
L6732
Figure 29. HTSSOP16 mechanical data
TSSOP16 EXPOSED PAD MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D D1 E E1 E2 e K L 0 0.45 0.60 6.2 4.3 0.8 0.19 0.09 4.9 5 3.0 6.4 4.4 3.0 0.65 8 0.75 0 0.018 0.024 6.6 4.5 0.244 0.169 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 0.031 0.007 0.004 0.193 0.197 0.118 0.252 0.173 0.118 0.0256 8 0.030 0.260 0.177 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 inch
7419276A
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Revision history
9
Revision history
Table 10.
Date 20-Dec-2005 24-Jan-2006 29-May-2006 26-Jun-2006 25-Sep-2006
Revision history
Revision 1 2 3 4 5 Initial release Improved description of Soft-Start, in case of Pre-bias Start-Up New template, thermal data updated Note page 10 deleted New DemoBoards Section 7: L6732 demoboards on page 26 Changes
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L6732
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